Semiconductor integrated circuits employ output driver circuits to drive capacitive loads. One example use of an output driver circuit is to drive row select lines in a semiconductor memory array.
Conventional output driver circuits utilize complementary metal-on-semiconductor (CMOS) technology. A conventional CMOS output circuit includes a p-channel MOS (PMOS) transistor coupled between voltage and an output node, and an n-channel MOS (NMOS) transistor coupled between the output node and ground. The CMOS design enables the PMOS transistor to be "on" while the NMOS transistor is "off", and vice versa, in response to a single input signal. When the PMOS transistor is "on" and the NMOS transistor is "off", the CMOS driver circuit outputs a voltage. Conversely, when the PMOS transistor is "off" and the NMOS transistor is "on", the output of the CMOS driver circuit is grounded.
One drawback inherent in the design of conventional CMOS output driver circuits is that during the rail-to-rail voltage swing at the input, there exists a period of time when both the PMOS and NMOS transistors are "on". This dual activation condition causes a phenomenon known as "crossing current" which wastes power.
This invention provides a high speed, low-to-high voltage CMOS driver circuit which eliminates or substantially reduces crossing current in an effort to conserve power.